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rev. a - may 7, 1999 1 tsc80251g2d 8/16-bit microcontroller with serial communication interfaces 1. description the tsc80251g2d products are derivatives of the t emic microcontroller family based on the 8/16-bit c251 architecture. this family of products is tailored to 8/16-bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. the architecture can provide a significant code size reduction when compiling c programs while fully preserving the legacy of c51 assembly routines. the tsc80251g2d derivatives are pin and software compatible with standard 80c51/fx/rx/rx+ with extended on-chip data memory (1 kbyte ram) and up to 256 kbytes of external code and data. additionally, the tsc83251g2d and tsc87251g2d provide on-chip code memory: 32 kbytes rom and 32 kbytes eprom/ otprom respectively. they provide transparent enhancements to intels 8xc251sx family with an additional synchronous serial link controller (sslc supporting i 2 c, m wire and spi protocols), a keyboard interrupt interface, a dedicated baud rate generator for uart, and power management features. tsc80251g2d derivatives are optimized for speed and for low power consumption on a wide voltage range. note: this datasheet provides the technical description of the tsc80251g2d derivatives. for further information on the device usage, please request the tsc80251 programmers guide and the tsc80251g1d design guide. 2. typical applications l isdn terminals l high-speed modems l pabx (soho) l line cards l dvd rom and players l printers l plotters l scanners l banking machines l barcode readers l smart cards readers l high-end digital monitors l high-end joysticks
2 rev. a - may 7, 1999 tsc80251g2d 3. features l pin and software compatibility with standard 80c51 products and 80c51fx/rx/rx+ l plug-in replacement of intels 8xc251sx l c251 core: intels mcs ? 251 d-step compliance 40-byte register file registers accessible as bytes, words or dwords three-stage instruction pipeline 16-bit internal code fetch l enriched c51 instruction set 16-bit and 32-bit alu compare and conditional jump instructions expanded set of move instructions l linear addressing l 1 kbyte of on-chip ram l external memory space (code/data) programmable from 64 kbytes to 256 kbytes l tsc87251g2d: 32 kbytes of on-chip eprom/ otprom single pulse programming algorithm l tsc83251g2d: 32 kbytes of on-chip masked rom l tsc80251g2d: romless version l four 8-bit parallel i/o ports (ports 0, 1, 2 and 3 of the standard 80c51) l serial i/o port: full duplex uart (80c51 compatible) with independent baud rate generator l sslc: synchronous serial link controller i 2 c multi-master protocol m wire and spi master and slave protocols l three 16-bit timers/counters (timers 0, 1 and 2 of the standard 80c51) l ewc: event and waveform controller compatible with intels programmable counter array (pca) common 16-bit timer/counter reference with four possible clock sources (fosc/4, fosc/12, timer 1 and external input) five modules, each with four programmable modes: - 16-bit software timer/counter - 16-bit timer/counter capture input and software pulse measurement - high-speed output and 16-bit software pulse width modulation (pwm) - 8-bit hardware pwm without overhead 16-bit watchdog timer/counter capability l secure 14-bit hardware watchdog timer l power management power-on reset (integrated on the chip) power-off flag (cold and warm resets) software programmable system clock idle mode power-down mode l keyboard interrupt interface on port 1 l non maskable interrupt input (nmi) l real-time wait states inputs (wait#/await#) l once mode and full speed real-time in-circuit emulation support (third party vendors) l high speed versions: 4.5 to 5.5 v 16 mhz and 24 mhz typical operating current: 35 ma @ 24 mhz 24 ma @ 16 mhz typical power-down current: 2 m a l low voltage version: 2.7 to 5.5 v 16 mhz typical operating current: 11 ma @ 3v typical power-down current: 1 m a l temperature ranges: commercial (0 cto+70 c) industrial (-40 cto+85 c) option: extended range (-55 c to +125 c) l packages: pdil 40, plcc 44 and vqfp 44 cdil 40 and cqpj 44 with window options: known good dice and ceramic packages
rev. a - may 7, 1999 3 tsc80251g2d 4. block diagram figure 1. tsc80251g2d block diagram 16-bit memory code 16-bit memory address 16-bit instruction bus 24-bit program counter bus 8-bit data bus 24-bit data address bus 8-bit internal bus peripheral interface unit vdd vss vss1 p3(a16) p1(a17) p2(a15-8) p0(ad7-0) rst xtal2 xtal1 nmi ea#/vpp ale/prog# psen# timers 0, 1 and 2 event and waveform controller i 2 c/spi/ m wire controller watchdog timer power management clock unit clock system prescaler keyboard interface bus interface unit cpu ports 0-3 interrupt handler unit ram 1 kbyte rom uart baud rate generator await# eprom otprom 32 kbytes vss2
4 rev. a - may 7, 1999 tsc80251g2d 5. pin description 5.1 pinout figure 2. tsc80251g2d 40-pin dip package figure 3. tsc80251g2d 44-pin plcc package tsc80251g2d 7 8 9 10 11 12 13 14 16 15 17 18 19 20 1 2 3 4 5 6 34 33 32 31 30 29 28 27 25 26 24 23 22 21 40 39 38 37 36 35 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1 p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# p2.7/a15 p2.6/a14 p2.5/a13 p3.7/a16/rd# xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# tsc80251g2d p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 39 38 37 36 35 34 33 32 29 30 31 7 8 9 10 11 12 13 14 17 16 15 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 44 43 42 41 40 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# nmi p2.7/a15 p2.6/a14 p2.5/a13 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd await# p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1 1
rev. a - may 7, 1999 5 tsc80251g2d figure 4. tsc80251g2d 44-pin vqfp package table 1. tsc80251g2d pin assignment dip plcc vqfp name dip plcc vqfp name 1 39 vss1 23 17 vss2 1 2 40 p1.0/t2 21 24 18 p2.0/a8 2 3 41 p1.1/t2ex 22 25 19 p2.1/a9 3 4 42 p1.2/eci 23 26 20 p2.2/a10 4 5 43 p1.3/cex0 24 27 21 p2.3/a11 5 6 44 p1.4/cex1/ss# 25 28 22 p2.4/a12 6 7 1 p1.5/cex2/miso 26 29 23 p2.5/a13 7 8 2 p1.6/cex3/scl/sck/wait# 27 30 24 p2.6/a14 8 9 3 p1.7/a17/cex4/sda/mosi/wclk 28 31 25 p2.7/a15 9 10 4 rst 29 32 26 psen# 10 11 5 p3.0/rxd 30 33 27 ale/prog# 12 6 await# 34 28 nmi 11 13 7 p3.1/txd 31 35 29 ea#/vpp 12 14 8 p3.2/int0# 32 36 30 p0.7/ad7 13 15 9 p3.3/int1# 33 37 31 p0.6/ad6 14 16 10 p3.4/t0 34 38 32 p0.5/ad5 15 17 11 p3.5/t1 35 39 33 p0.4/ad4 16 18 12 p3.6/wr# 36 40 34 p0.3/ad3 17 19 13 p3.7/a16/rd# 37 41 35 p0.2/ad2 18 20 14 xtal2 38 42 36 p0.1/ad1 19 21 15 xtal1 39 43 37 p0.0/ad0 20 22 16 vss 40 44 38 vdd tsc80251g2d p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 33 32 31 30 29 28 27 26 23 24 25 1 2 3 4 5 6 7 8 11 10 9 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# nmi p2.7/a15 p2.6/a14 p2.5/a13 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd await# p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1
6 rev. a - may 7, 1999 tsc80251g2d 5.2 signals table 2. product name signal descriptions signal name type description alternate function a17 o 18 th address bit output to memory as 18th external address bit (a17) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 15). p1.7 a16 o 17 th address bit output to memory as 17th external address bit (a16) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 15). p3.7 a15:8 (1) o address lines upper address lines for the external bus. p2.7:0 ad7:0 (1) i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals the start of an external bus cycle and indicates that valid address information are available on lines a16/a17 and a7:0. an external latch can use ale to demultiplex the address from address/data bus. await# i real-time asynchronous wait states input when this pin is active (low level), the memory cycle is stretched until it becomes high. when using the product name as a pin-for-pin replacement for a 8xc51 product, await# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). not available on dip package. cex4:0 i/o pca input/output pins cexx are input signals for the pca capture mode and output signals for the pca compare and pwm modes. p1.7:3 ea# i external access enable ea# directs program memory accesses to on-chip or off-chip code memory. for ea#= 0, all program memory accesses are off-chip. for ea#= 1, an access is on-chip rom if the address is within the range of the on-chip rom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without rom on-chip, ea# must be strapped to ground. eci o pca external clock input eci is the external clock input to the 16-bit pca timer. p1.2 miso i/o spi master input slave output line when spi is in master mode, miso receives data from the slave peripheral. when spi is in slave mode, miso outputs data to the master controller. p1.5 mosi i/o spi master output slave input line when spi is in master mode, mosi outputs data to the slave peripheral. when spi is in slave mode, mosi receives data from the master controller. p1.7 int1:0# i external interrupts 0 and 1 int1#/int0# inputs set ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits it1:0 are cleared, bits ie1:0 are set by a low level on int1#/int0#. p3.3:2 nmi i non maskable interrupt holding this pin high for 24 oscillator periods triggers an interrupt. when using the product name as a pin-for-pin replacement for a 8xc51 product, nmi can be unconnected without loss of compatibility or power consumption increase (on-chip pull- down). not available on dip package. p0.0:7 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any paraitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0
rev. a - may 7, 1999 7 tsc80251g2d p1.0:7 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. p1 provides interrupt capability for a keyboard interface. p2.0:7 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.0:7 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. prog# i programming pulse input the programming pulse is applied to this input for programming the on-chip eprom/ otprom. psen# o program store enable/read signal output psen# is asserted for a memory address range that depends on bits rd0 and rd1 in uconfig0 byte (see table 13, page 15). rd# o read or 17 th address bit (a16) read signal output to external data memory depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 15). p3.7 rst i reset input to the chip holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and vdd. asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 scl i/o i 2 c serial clock when i 2 c controller is in master mode, scl outputs the serial clock to slave peripherals. when i 2 c controller is in slave mode, scl receives clock from the master controller. p1.6 sck i/o spi serial clock when spi is in master mode, sck outputs clock to the slave peripheral. when spi is in slave mode, sck receives clock from the master controller. p1.6 sda i/o i 2 c serial data sda is the bidirectional i 2 c data line. p1.7 ss# i spi slave select input when in slave mode, ss# enables the slave mode. p1.4 t1:0 i/o timer 1:0 external clock inputs when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. t2 i/o timer 2 clock input/output for the timer 2 capture mode, t2 is the external clock input. for the timer 2 clock-out mode, t2 is the clock output. p1.0 t2ex i timer 2 external input in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto- reload mode, a falling edge causes the timer 2 register to be reloaded. in the up-down counter mode, this signal determines the count direction: 1= up, 0= down. p1.1 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 vdd pwr digital supply voltage connect this pin to +5v or +3v supply voltage. vpp i programming supply voltage the programming supply voltage is applied to this input for programming the on-chip eprom/ otprom. signal name type description alternate function
8 rev. a - may 7, 1999 tsc80251g2d note: 1. the description of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the non-page mode chip configuration. if the chip is configured in page mode operation, port 0 carries the lower address bits (a7:0) while port 2 carries the upper address bits (a15:8) and the data (d7:0). vss gnd circuit ground connect this pin to ground. vss1 gnd secondary ground 1 this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the tsc80251g2d as a pin-for-pin replacement for a 8xc51 product, vss1 can be unconnected without loss of compatibility. not available on dip package. vss2 gnd secondary ground 2 this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the tsc80251g2d as a pin-for-pin replacement for a 8xc51 product, vss2 can be unconnected without loss of compatibility. not available on dip package. wait# i real-time synchronous wait states input the real-time wait# input is enabled by setting rtwe bit in wcon (s:a7h). during bus cycles, the external memory system can signal system ready to the microcontroller in real time by controlling the wait# input signal. p1.6 wclk o wait clock output the real-time wclk output is enabled by setting rtwce bit in wcon (s:a7h). when enabled, the wclk output produces a square wave signal with a period of one half the oscillator frequency. p1.7 wr# o write write signal output to external memory. p3.6 xtal1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal timing. xtal2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. signal name type description alternate function
rev. a - may 7, 1999 9 tsc80251g2d 6. address spaces the tsc80251g2d derivatives implement four different address spaces: l on-chip rom program/code memory (not present in romless devices) l on-chip ram data memory l special function registers (sfrs) l configuration array 6.1 program/code memory the tsc83251g2d and tsc87251g2d implement 32 kbytes of on-chip program/code memory. figure 5 shows the split of the internal and external program/code memory spaces. if ea# is tied to a high level, the 32-kbyte on-chip program memory is mapped in the lower part of segment ff: where the c251 core jumps after reset. the rest of the program/code memory space is mapped to the external memory. if ea# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. the tsc83251g2d products provide the internal program/code memory in a masked rom memory while the tsc87251g2d products provide it in an eprom memory. for the tsc80251g2d products, there is no internal program/code memory and ea# must be tied to a low level. figure 5. program/code memory mapping notes: special care should be taken when the program counter (pc) increments: 1. if the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight bytes of the on-chip rom (ff:7ff8h-ff:7fffh). because of its pipeline capability, the tsc80251g2d derivative may attempt to prefetch code from external memory (at an address above ff:7fffh) and thereby disrupt i/o ports 0 and 2. fetching code constants from these 8 bytes does not affect ports 0 and 2. 2. when pc reaches the end of segment ff:, it loops to the reset address ff:0000h (for compatibility with the c51 architecture). when pc increments beyond the end of segment fe:, it continues at the reset address ff:0000h (linearity). when pc increments beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area). on-chip rom/eprom code memory program/code segments program/code external memory space 32 kbytes ea#= 0 ea#= 1 32 kbytes 32 kbytes reserved 64 kbytes 128 kbytes ff:ffffh ff:8000h ff:7fffh ff:0000h fe:ffffh fe:0000h fd:ffffh 01:ffffh 01:0000h 02:0000h 00:ffffh 00:0000h
10 rev. a - may 7, 1999 tsc80251g2d 6.2 data memory the tsc80251g2d derivatives implement 1 kbyte of on-chip data ram. figure 6 shows the split of the internal and external data memory spaces. this memory is mapped in the data space just over the 32 bytes of registers area (see tsc80251 programmers guide). hence, the part of the on-chip ram located from 20h to ffh is bit addressable. this on-chip ram is not accessible through the program/code memory space. for faster computation with the on-chip rom/eprom code of the tsc83251g2d/tsc87251g2d, its upper 16 kbytes are also mapped in the upper part of the region 00: if the on-chip code memory map configuration bit is cleared (emap# bit in uconfig1 byte, see figure 8). however, if ea# is tied to a low level, the tsc80251g2d derivative is running as a romless product and the code is actually fetched in the corresponding external memory (i.e. the upper 16 kbytes of the lower 32 kbytes of the segment ff:). if emap# bit is set, the on-chip rom is not accessible through the region 00:. all the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external memory. figure 6. data memory mapping 6.3 special function registers the special function registers (sfrs) of the tsc80251g2d derivatives fall into the categories detailed in table 3 to table 11. sfrs are placed in a reserved on-chip memory region s: which is not represented in the data memory mapping (figure 6). the relative addresses within s: of these sfrs are provided together with their reset values in table 12. they are upward compatible with the sfrs of the standard 80c51 and the intels 80c251sx family. in this table, the c251 core registers are identified by note 1 and are described in the tsc80251 programmers guide. the other sfrs are described in the tsc80251g1d design guide. all the sfrs are bit-addressable using the c251 instruction set. on-chip rom/eprom code memory data segments data external memory space 16 kbytes ea#= 0 ea#= 1 32 kbytes 32 kbytes reserved 64 kbytes ? 47 kbytes ff:ffffh ff:8000h ff:7fffh ff:0000h fe:ffffh fe:0000h fd:ffffh 01:ffffh 01:0000h 02:0000h 00:ffffh 00:0420h 32 bytes reg. ram data 1 kbyte 16 kbytes 00:c000h 00:bfffh emap#= 1 emap#= 0 16 kbytes 64 kbytes
rev. a - may 7, 1999 11 tsc80251g2d table 3. c251 core sfrs note: 1. these sfrs can also be accessed by their corresponding registers in the register file. table 4. i/o port sfrs table 5. timers sfrs table 6. serial i/o port sfrs table 7. sslc sfrs mnemonic name mnemonic name acc (1) accumulator sph (1) stack pointer high - msb of spx b (1) b register dpl (1) data pointer low byte - lsb of dptr psw program status word dph (1) data pointer high byte - msb of dptr psw1 program status word 1 dpxl (1) data pointer extended low byte of dpx - region number sp (1) stack pointer - lsb of spx mnemonic name mnemonic name p0 port 0 p2 port 2 p1 port 1 p3 port 3 mnemonic name mnemonic name tl0 timer/counter 0 low byte tmod timer/counter 0 and 1 modes th0 timer/counter 0 high byte t2con timer/counter 2 control tl1 timer/counter 1 low byte t2mod timer/counter 2 mode th1 timer/counter 1 high byte rcap2l timer/counter 2 reload/capture low byte tl2 timer/counter 2 low byte rcap2h timer/counter 2 reload/capture high byte th2 timer/counter 2 high byte wdtrst watchdog timer reset tcon timer/counter 0 and 1 control mnemonic name mnemonic name scon serial control saddr slave address sbuf serial data buffer brl baud rate reload saden slave address mask bdrcon baud rate control mnemonic name mnemonic name sscon synchronous serial control ssadr synchronous serial address ssdat synchronous serial data ssbr synchronous serial bit rate sscs synchronous serial control and status
12 rev. a - may 7, 1999 tsc80251g2d table 8. event waveform control sfrs table 9. system management sfrs table 10. interrupt sfrs table 11. keyboard interface sfrs mnemonic name mnemonic name ccon ewc-pca timer/counter control ccap0l ewc-pca compare capture module 0 low register cmod ewc-pca timer/counter mode ccap1l ewc-pca compare capture module 1 low register cl ewc-pca timer/counter low register ccap2l ewc-pca compare capture module 2 low register ch ewc-pca timer/counter high register ccap3l ewc-pca compare capture module 3 low register ccapm0 ewc-pca timer/counter mode 0 ccap4l ewc-pca compare capture module 4 low register ccapm1 ewc-pca timer/counter mode 1 ccap0h ewc-pca compare capture module 0 high register ccapm2 ewc-pca timer/counter mode 2 ccap1h ewc-pca compare capture module 1 high register ccapm3 ewc-pca timer/counter mode 3 ccap2h ewc-pca compare capture module 2 high register ccapm4 ewc-pca timer/counter mode 4 ccap3h ewc-pca compare capture module 3 high register ccap4h ewc-pca compare capture module 4 high register mnemonic name mnemonic name pcon power control ckrl clock reload powm power management wcon synchronous real-time wait state control mnemonic name mnemonic name ie0 interrupt enable control 0 ipl0 interrupt priority control low 0 ie1 interrupt enable control 1 iph1 interrupt priority control high 1 iph0 interrupt priority control high 0 ipl1 interrupt priority control low 1 mnemonic name mnemonic name p1ie port 1 input interrupt enable p1ls port 1 level selection p1f port 1 flag
rev. a - may 7, 1999 13 tsc80251g2d table 12. sfr addresses and reset values notes: 1. these registers are described in the tsc80251 programmers guide (c251 core registers). 2. in i 2 c and spi modes, sscon is splitted in two separate registers. sscon reset value is 0000 0000 in i 2 c mode and 0000 0100 in spi mode. 3. in read and write modes, sscs is splitted in two separate registers. sscs reset value is 1111 1000 in read mode and 0000 0000 in write mode. 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 ffh f0h b (1) 0000 0000 f7h e8h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 efh e0h acc (1) 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw (1) 0000 0000 psw1 (1) 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h c7h b8h ipl0 x000 0000 saden 0000 0000 sph (1) 0000 0000 bfh b0h p3 1111 1111 ie1 xx0x xxx0 ipl1 xx0x xxx0 iph1 xx0x xxx0 iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 wdtrst 1111 1111 wcon xxxx xx00 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 p1ls 0000 0000 p1ie 0000 0000 p1f 0000 0000 9fh 90h p1 1111 1111 ssbr 0000 0000 sscon (2) sscs (3) ssdat 0000 0000 ssadr 0000 0000 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckrl 0000 1000 powm 0xxx xxxx 8fh 80h p0 1111 1111 sp (1) 0000 0111 dpl (1) 0000 0000 dph (1) 0000 0000 dpxl (1) 0000 0001 pcon 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
14 rev. a - may 7, 1999 tsc80251g2d 6.4 configuration bytes the tsc80251g2d derivatives provide user design flexibility by configuring certain operating features at device reset. these features fall into the following categories: external memory interface (page mode, address bits, programmed wait states and the address range for rd#, wr#, and psen#) source mode/binary mode opcodes selection of bytes stored on the stack by an interrupt mapping of the upper portion of on-chip code memory to region 00: two user configuration bytes uconfig0 (see figure 7) and uconfig1 (see figure 8) provide the information. when ea# is tied to a low level, the configuration bytes are fetched from the external address space. the tsc80251g2d derivatives reserve the top eight bytes of the memory address space (ff:fff8h-ff:ffffh) for an external 8-byte configuration array. only two bytes are actually used: uconfig0 at ff:fff8h and uconfig1 at ff:fff9h. for the mask rom devices, configuration information is stored in on-chip memory (see rom verifying). when ea# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory. uconfig0 configuration byte 0 notes: 1. uconfig0 is fetched twice so it can be properly read both in page or non-page modes. if p2.1 is cleared during the first data fetch, a page mode configuration is used, otherwise the subsequent fetches are performed in non-page mode. 2. this selection provides compatibility with the standard 80c51 hardware which is multiplexing the address lsb and the data on port 0. figure 7. configuration byte 0 76543210 - wsa1# wsa0# xale# rd1 rd0 page# src bit number bit mnemonic description 7- reserved set this bit when writing to uconfig0. 6 wsa1# wait state a bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (all regions except 01:). wsa1# wsa0# number of wait states 00 3 01 2 10 1 11 0 5 wsa0# 4 xale# extend ale bit clear to extend the duration of the ale pulse from t osc to 3t osc. set to minimize the duration of the ale pulse to 1t osc . 3 rd1 memory signal select bits specify a 18-bit, 17-bit or 16-bit external address bus and the usage of rd#, wr# and psen# signals (see table 13). 2 rd0 1 page# page mode select bit (1) clear to select the faster page mode with a15:8/d7:0 on port 2 and a7:0 on port 0. set to select the non-page mode (2) with a15:8 on port 2 and a7:0/d7:0 on port 0. 0 src source mode/binary mode select bit clear to select the binary mode. set to select the source mode.
rev. a - may 7, 1999 15 tsc80251g2d uconfig1 configuration byte 1 notes: 1. the csize is only available on eprom/otprom products. 2. two or four bytes are transparently popped according to intr when using the reti instruction. intr must be set if interrupts are used with code executing outside region ff:. 3. use only for step a compatibility; set this bit when wsb1:0# are used. figure 8. configuration byte 1 table 13. address ranges and usage of rd#, wr# and psen# signals note: 1. this selection provides compatibility with the standard 80c51 hardware which has separate external memory spaces for data and code. 76543210 csize - - intr wsb wsb1# wsb0# emap# bit number bit mnemonic description 7 csize tsc87251g2d on-chip code memory size bit (1) clear to select 16 kbytes of on-chip code memory (tsc87251g1d product). set to select 32 kbytes of on-chip code memory (tsc87251g2d product). - tsc80251g2d tsc83251g2d reserved set this bit when writing to uconfig1. 6- reserved set this bit when writing to uconfig1. 5- reserved set this bit when writing to uconfig1. 4 intr interrupt mode bit (2) clear so that the interrupts push two bytes onto the stack (the two lower bytes of the pc register). set so that the interrupts push four bytes onto the stack (the three bytes of the pc register and the psw1 register). 3 wsb wait state b bit (3) clear to generate one wait state for memory region 01:. set for no wait states for memory region 01:. 2 wsb1# wait state b bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (only region 01:). wsb1# wsb0# number of wait states 00 3 01 2 10 1 11 0 1 wsb0# 0 emap# on-chip code memory map bit clear to map the upper 16 kbytes of on-chip code memory (at ff:4000h-ff:7fffh) to the data space (at 00:c000h-00:ffffh). set not to map the upper 16 kbytes of on-chip code memory (at ff:4000h-ff:7fffh) to the data space. rd1 rd0 p1.7 p3.7/rd# psen# wr# external memory 0 0 a17 a16 read signal for all external memory locations write signal for all external memory locations 256 kbytes 0 1 i/o pin a16 read signal for all external memory locations write signal for all external memory locations 128 kbytes 1 0 i/o pin i/o pin read signal for all external memory locations write signal for all external memory locations 64 kbytes 1 1 i/o pin read signal for regions 00: and 01: read signal for regions fe: and ff: write signal for all external memory locations 2 64 kbytes (1)
rev. a - may 7, 1999 16 tsc80251g2d 7. instruction set summary this section contains tables that summarize the instruction set. for each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). there are two concurrent processes limiting the effective instruction throughput: l instruction fetch l instruction execution table 20 to table 34 assume code executing from on-chip memory, then the cpu is fetching 16-bit at a time and this is never limiting the execution speed. if the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. however, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). the maximum average instruction throughput is provided by table 14 depending on the external memory configuration (from page mode to non-page mode and the maximum number of wait states). if the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. table 14. minimum number of states per instruction for given average sizes if the average execution time of the considered instructions is larger than the number of states given by table 14, this larger value will prevail as the limiting factor. otherwise, the value from table 14 must be taken. this is providing a fair estimation of the execution speed but only the actual code execution can provide the final value. 7.1 notation for instruction operands table 15 to table 19 provide notation for instruction operands. table 15. notation for direct addressing table 16. notation for immediate addressing average size of instructions (bytes) page mode (states) non-page mode (states) 0 wait state 1 wait state 2 wait states 3 wait states 4 wait states 1123456 224681012 3 3 6 9 12 15 18 4 4 8 12162024 5 5 10 15 20 25 30 direct address description c251 c51 dir8 a direct 8-bit address. this can be a memory address (00h-7fh) or a sfr address (80h- ffh). it is a byte (default), word or double word depending on the other operand. 33 dir16 a 16-bit memory address (00:0000h-00:ffffh) used in direct addressing. 3 immediate address description c251 c51 #data an 8-bit constant that is immediately addressed in an instruction 33 #data16 a 16-bit constant that is immediately addressed in an instruction 3 #0data16 #1data16 a 32-bit constant that is immediately addressed in an instruction. the upper word is filled with zeros (#0data16) or ones (#1data16). 3 #short a constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. 3
17 rev. a - may 7, 1999 tsc80251g2d table 17. notation for bit addressing table 18. notation for destination in control instructions table 19. notation for register operands direct address description c251 c51 bit51 a directly addressed bit (bit number= 00h-ffh) in memory or an sfr. bits 00h-7fh are the 128 bits in byte locations 20h-2fh in the on-chip ram. bits 80h-ffh are the 128 bits in the 16 sfrs with addresses that end in 0h or 8h, s:80h, s:88h, s:90h,..., s:f0h, s:f8h. 3 bit a directly addressed bit in memory locations 00:0020h-00:007fh or in any defined sfr. 3 direct address description c251 c51 rel a signed (twos complement) 8-bit relative address. the destination is -128 to +127 bytes relative to the next instructions first byte. 33 addr11 an 11-bit target address. the target is in the same 2-kbyte block of memory as the next instructions first byte. 3 addr16 a 16-bit target address. the target can be anywhere within the same 64-kbyte region as the next instructions first byte. 3 addr24 a 24-bit target address. the target can be anywhere within the 16-mbyte address space. 3 register description c251 c51 @ri a memory location (00h-ffh) addressed indirectly via byte registers r0 or r1 3 rn n byte register r0-r7 of the currently selected register bank byte register index: n= 0-7 3 rm rmd rms m, md, ms byte register r0-r15 of the currently selected register file destination register source register byte register index: m, md, ms= 0-15 3 wrj wrjd wrjs @wrj @wrj +dis16 j, jd, js word register wr0, wr2, ..., wr30 of the currently selected register file destination register source register a memory location (00:0000h-00:ffffh) addressed indirectly through word register wr0- wr30, is the target address for jump instructions. a memory location (00:0000h-00:ffffh) addressed indirectly through word register (wr0- wr30) + 16-bit signed (twos complement) displacement value word register index: j, jd, js= 0-30 3 drk drkd drks @drk @drk +dis16 k, kd, ks dword register dr0, dr4, ..., dr28, dr56, dr60 of the currently selected register file destination register source register a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register dr0- dr28, dr56 and dr60, is the target address for jump instruction a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register (dr0- dr28, dr56, dr60) + 16-bit (twos complement) signed displacement value dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60 3
rev. a - may 7, 1999 18 tsc80251g2d 7.2 size and execution time for instruction families table 20. summary of add and subtract instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 4. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). add add , dest opnd ? dest opnd + src opnd subtract sub , dest opnd ? dest opnd - src opnd add with carry addc , (a) ? (a) + src opnd + (cy) subtract with borrow subb , (a) ? (a) - src opnd - (cy) mnemonic , (1) comments binary mode source mode bytes states bytes states add a, rn register to acc 1 1 2 2 a, dir8 direct address to acc 2 1 (2) 21 (2) a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 add / sub rmd, rms byte register to/from byte register 3 2 2 1 wrjd, wrjs word register to/from word register 3 3 2 2 drkd, drks dword register to/from dword register 3 5 2 4 rm, #data immediate 8-bit data to/from byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to/from word register 5 4 4 3 drk, #0data16 16-bit unsigned immediate data to/from dword register 5 6 4 5 rm, dir8 direct address (on-chip ram or sfr) to/from byte register 4 3 (2) 32 (2) wrj, dir8 direct address (on-chip ram or sfr) to/from word register 4 4 3 3 rm, dir16 direct address (64k) to/from byte register 5 3 (3) 42 (3) wrj, dir16 direct address (64k) to/from word register 5 4 (4) 43 (4) rm, @wrj indirect address (64k) to/from byte register 4 3 (3) 32 (3) rm, @drk indirect address (16m) to/from byte register 4 4 (3) 33 (3) addc / subb a, rn register to/from acc with carry 1 1 2 2 a, dir8 direct address (on-chip ram or sfr) to/from acc with carry 21 (2) 21 (2) a, @ri indirect address to/from acc with carry 1 2 2 3 a, #data immediate data to/from acc with carry 2 1 2 1
19 rev. a - may 7, 1999 tsc80251g2d table 21. summary of increment and decrement instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. table 22. summary of compare instructions notes: 1. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 2. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 3. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). increment inc dest opnd ? dest opnd + 1 increment inc , dest opnd ? dest opnd + src opnd decrement dec dest opnd ? dest opnd - 1 decrement dec , dest opnd ? dest opnd - src opnd mnemonic , (1) comments binary mode source mode bytes states bytes states inc dec a acc by 1 1 1 1 1 rn register by 1 1 1 2 2 dir8 direct address (on-chip ram or sfr) by 1 2 2 (2) 22 (2) @ri indirect address by 1 1 3 2 4 inc dec rm, #short byte register by 1, 2, or 4 3 2 2 1 wrj, #short word register by 1, 2, or 4 3 2 2 1 inc drk, #short double word register by 1, 2, or 4 3 4 2 3 dec drk, #short double word register by 1, 2, or 4 3 5 2 4 inc dptr data pointer by 1 1 1 1 1 compare cmp , dest opnd - src opnd mnemonic , (2) comments binary mode source mode bytes states bytes states cmp rmd, rms register with register 3 2 2 1 wrjd, wrjs word register with word register 3 3 2 2 drkd, drks dword register with dword register 3 5 2 4 rm, #data register with immediate data 4 3 3 2 wrj, #data16 word register with immediate 16-bit data 5 4 4 3 drk, #0data16 dword register with zero-extended 16-bit immediate data 5 6 4 5 drk, #1data16 dword register with one-extended 16-bit immediate data 5 6 4 5 rm, dir8 direct address (on-chip ram or sfr) with byte register 4 3 (1) 32 (1) wrj, dir8 direct address (on-chip ram or sfr) with word register 4 4 3 3 rm, dir16 direct address (64k) with byte register 5 3 (2) 42 (2) wrj, dir16 direct address (64k) with word register 5 4 (3) 43 (3) rm, @wrj indirect address (64k) with byte register 4 3 (2) 32 (2) rm, @drk indirect address (16m) with byte register 4 4 (2) 33 (2)
rev. a - may 7, 1999 20 tsc80251g2d table 23. summary of logical instructions (1/2) notes: 1. logical instructions that affect a bit are in table 29. 2. a shaded cell denotes an instruction in the c51 architecture. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. 5. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). logical and (1) anl , dest opnd ? dest opnd l src opnd logical or (1) orl , dest opnd ? dest opnd v src opnd logical exclusive or (1) xrl , dest opnd ? dest opnd " src opnd clear (1) clr a (a) ? 0 complement (1) cpl a (a) ?? (a) rotate left rl a (a) n+1 ? (a) n , n= 0..6 (a) 0 ? (a) 7 rotate left carry rlc a (a) n+1 ? (a) n , n= 0..6 (cy) ? (a) 7 (a) 0 ? (cy) rotate right rr a (a) n-1 ? (a) n , n= 7..1 (a) 7 ? (a) 0 rotate right carry rrc a (a) n-1 ? (a) n , n= 7..1 (cy) ? (a) 0 (a) 7 ? (cy) mnemonic , (1) comments binary mode source mode bytes states bytes states anl orl xrl a, rn register to acc 1 1 2 2 a, dir8 direct address (on-chip ram or sfr) to acc 2 1 (3) 21 (3) a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 dir8, a acc to direct address 2 2 (4) 22 (4) dir8, #data immediate 8-bit data to direct address 3 3 (4) 33 (4) rmd, rms byte register to byte register 3 2 2 1 wrjd, wrjs word register to word register 3 3 2 2 rm, #data immediate 8-bit data to byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to word register 5 4 4 3 rm, dir8 direct address (on-chip ram or sfr) to byte register 4 3 (3) 32 (3) wrj, dir8 direct address (on-chip ram or sfr) to word register 4 4 3 3 rm, dir16 direct address (64k) to byte register 5 3 (5) 42 (5) wrj, dir16 direct address (64k) to word register 5 4 (6) 43 (6) rm, @wrj indirect address (64k) to byte register 4 3 (5) 32 (5) rm, @drk indirect address (16m) to byte register 4 4 (5) 33 (5) clr a clear acc 1 1 1 1 cpl a complement acc 1 1 1 1 rl a rotate acc left 1 1 1 1 rlc a rotate acc left through cy 1 1 1 1 rr a rotate acc right 1 1 1 1 rrc a rotate acc right through cy 1 1 1 1
21 rev. a - may 7, 1999 tsc80251g2d table 24. summary of logical instructions (2/2) note: 1. a shaded cell denotes an instruction in the c51 architecture. table 25. summary of multiply, divide and decimal-adjust instructions note: 1. a shaded cell denotes an instruction in the c51 architecture. shift left logical sll 0 ? 0 n+1 ? n , n= 0..msb-1 (cy) ? msb shift right arithmetic sra msb ? msb n-1 ? n , n= msb..1 (cy) ? 0 shift right logical srl msb ? 0 n-1 ? n , n= msb..1 (cy) ? 0 swap swap a a 3:0 a 7:4 mnemonic , (1) comments binary mode source mode bytes states bytes states sll rm shift byte register left through the msb 3 2 2 1 wrj shift word register left through the msb 3 2 2 1 sra rm shift byte register right 3 2 2 1 wrj shift word register right 3 2 2 1 srl rm shift byte register left 3 2 2 1 wrj shift word register left 3 2 2 1 swap a swap nibbles within acc 1 2 1 2 multiply mul ab (b:a) ? (a) (b) mul , extended dest opnd ? dest opnd src opnd divide div ab (a) ? quotient ((a) (b)) (b) ? remainder ((a) (b)) divide div , ext. dest opnd high ? quotient (dest opnd src opnd) ext. dest opnd low ? remainder (dest opnd src opnd) decimal-adjust acc da a if [[(a) 3:0 >9] [(ac)= 1]] for addition (bcd) then (a) 3:0 ? (a) 3:0 + 6 !affects cy; if [[(a) 7:4 >9] [(cy)= 1]] then (a) 7:4 ? (a) 7:4 +6 mnemonic , (1) comments binary mode source mode bytes states bytes states mul ab multiply a and b 1 5 1 5 rmd, rms multiply byte register and byte register 3 6 2 5 wrjd, wrjs multiply word register and word register 3 12 2 11 div ab divide a and b 1 10 1 10 rmd, rms divide byte register and byte register 3 11 2 10 wrjd, wrjs divide word register and word register 3 21 2 20 da a decimal adjust acc 1 1 1 1
rev. a - may 7, 1999 22 tsc80251g2d table 26. summary of move instructions (1/3) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. extended memory addressed is in the region specified by dpxl (reset value= 01h). 3. if this instruction addresses external memory location, add n+1 to the number of states (n: number of wait states). 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). table 27. summary of move instructions (2/3) notes: 1. instructions that move bits are in table 29. 2. move instructions from the c51 architecture. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. apply note 3 for each dir8 operand. move to high word movh , dest opnd 31:16 ? src opnd move with sign extension movs , dest opnd ? src opnd with sign extend move with zero extension movz , dest opnd ? src opnd with zero extend move code movc a, (a) ? src opnd move extended movx , dest opnd ? src opnd mnemonic , (2) comments binary mode source mode bytes states bytes states movh drk, #data16 16-bit immediate data into upper word of dword register 5 3 4 2 movs wrj, rm byte register to word register with sign extension 3 2 2 1 movz wrj, rm byte register to word register with zeros extension 3 2 2 1 movc a, @a +dptr code byte relative to dptr to acc 1 6 (3) 16 (3) a, @a +pc code byte relative to pc to acc 1 6 (3) 16 (3) movx a, @ri extended memory (8-bit address) to acc (2) 1415 a, @dptr extended memory (16-bit address) to acc (2) 13 (4) 13 (4) @ri, a acc to extended memory (8-bit address) (2) 1414 @dptr, a acc to extended memory (16-bit address) (2) 14 (3) 14 (3) move (1) mov , dest opnd ? src opnd mnemonic , (2) comments binary mode source mode bytes states bytes states mov a, rn register to acc 1 1 2 2 a, dir8 direct address (on-chip ram or sfr) to acc 2 1 (3) 21 (3) a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 rn, a acc to register 1 1 2 2 rn, dir8 direct address (on-chip ram or sfr) to register 2 1 (3) 32 (3) rn, #data immediate data to register 2 1 3 2 dir8, a acc to direct address (on-chip ram or sfr) 2 2 (3) 22 (3) dir8, rn register to direct address (on-chip ram or sfr) 2 2 (3) 33 (3) dir8, dir8 direct address to direct address (on-chip ram or sfr) 3 3 (4) 33 (4) dir8, @ri indirect address to direct address (on-chip ram or sfr) 2 3 (3) 34 (3) dir8, #data immediate data to direct address (on-chip ram or sfr) 3 3 (3) 33 (3) @ri, a acc to indirect address 1 3 2 4 @ri, dir8 direct address (on-chip ram or sfr) to indirect address 2 3 (3) 34 (3) @ri, #data immediate data to indirect address 2 3 3 4 dptr, #data16 load data pointer with a 16-bit constant 3 2 3 2
23 rev. a - may 7, 1999 tsc80251g2d table 28. summary of move instructions (3/3) notes: 1. instructions that move bits are in table 29. 2. move instructions unique to the c251 architecture. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 5. if this instruction addresses external memory location, add 2(n+1) to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 4(n+2) to the number of states (n: number of wait states). move (1) mov , dest opnd ? src opnd mnemonic , (1) comments binary mode source mode bytes states bytes states mov rmd, rms byte register to byte register 3 2 2 1 wrjd, wrjs word register to word register 3 2 2 1 drkd, drks dword register to dword register 3 3 2 2 rm, #data immediate 8-bit data to byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to word register 5 3 4 2 drk, #0data16 zero-ext 16bit immediate data to dword register 5 5 4 4 drk, #1data16 one-ext 16bit immediate data to dword register 5 5 4 4 rm, dir8 direct address (on-chip ram or sfr) to byte register 4 3 (3) 32 (3) wrj, dir8 direct address (on-chip ram or sfr) to word register 4 4 3 3 drk, dir8 direct address (on-chip ram or sfr) to dword register 4 6 3 5 rm, dir16 direct address (64k) to byte register 5 3 (4) 42 (4) wrj, dir16 direct address (64k) to word register 5 4 (5) 43 (5) drk, dir16 direct address (64k) to dword register 5 6 (6) 45 (6) rm, @wrj indirect address (64k) to byte register 4 3 (4) 32 (4) rm, @drk indirect address (16m) to byte register 4 4 (4) 33 (4) wrjd, @wrjs indirect address (64k) to word register 4 4 (5) 33 (5) wrj, @drk indirect address (16m) to word register 4 5 (5) 34 (5) dir8, rm byte register to direct address (on-chip ram or sfr) 4 4 (3) 33 (3) dir8, wrj word register to direct address (on-chip ram or sfr) 4 5 3 4 dir8, drk dword register to direct address (on-chip ram or sfr) 4 7 3 6 dir16, rm byte register to direct address (64k) 5 4 (4) 43 (4) dir16, wrj word register to direct address (64k) 5 5 (5) 44 (5) dir16, drk dword register to direct address (64k) 5 7 (6) 46 (6) @wrj, rm byte register to indirect address (64k) 4 4 (4) 33 (4) @drk, rm byte register to indirect address (16m) 4 5 (4) 34 (4) @wrjd, wrjs word register to indirect address (64k) 4 5 (5) 34 (5) @drk, wrj word register to indirect address (16m) 4 6 (5) 35 (5) rm, @wrj +dis16 indirect with 16-bit displacement (64k) to byte register 5 6 (4) 45 (4) wrj, @wrj +dis16 indirect with 16-bit displacement (64k) to word register 5 7 (5) 46 (5) rm, @drk +dis24 indirect with 16-bit displacement (16m) to byte register 5 7 (4) 46 (4) wrj, @wrj +dis24 indirect with 16-bit displacement (16m) to word register 5 8 (5) 47 (5) @wrj +dis16, rm byte register to indirect with 16-bit displacement (64k) 5 6 (4) 45 (4) @wrj +dis16, wrj word register to indirect with 16-bit displacement (64k) 5 7 (5) 46 (5) @drk +dis24, rm byte register to indirect with 16-bit displacement (16m) 5 7 (4) 46 (4) @drk +dis24, wrj word register to indirect with 16-bit displacement (16m) 5 8 (5) 47 (5)
rev. a - may 7, 1999 24 tsc80251g2d table 29. summary of bit instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. clear bit clr dest opnd ? 0 set bit setb dest opnd ? 1 complement bit cpl dest opnd ?? bit and carry with bit anl cy, (cy) ? (cy) src opnd and carry with complement of bit anl cy, / (cy) ? (cy) ? src opnd or carry with bit orl cy, (cy) ? (cy) src opnd or carry with complement of bit orl cy, / (cy) ? (cy) ? src opnd move bit to carry mov cy, (cy) ? src opnd move bit from carry mov , cy dest opnd ? (cy) mnemonic , (1) comments binary mode source mode bytes states bytes states clr cy clear carry 1 1 1 1 bit51 clear direct bit 2 2 (3) 22 (3) bit clear direct bit 4 4 (3) 33 (3) setb cy set carry 1 1 1 1 bit51 set direct bit 2 2 (3) 22 (3) bit set direct bit 4 4 (3) 33 (3) cpl cy complement carry 1 1 1 1 bit51 complement direct bit 2 2 (3) 22 (3) bit complement direct bit 4 4 (3) 33 (3) anl cy, bit51 and direct bit to carry 2 1 (2) 21 (2) cy, bit and direct bit to carry 4 3 (2) 32 (2) cy, /bit51 and complemented direct bit to carry 2 1 (2) 21 (2) cy, /bit and complemented direct bit to carry 4 3 (2) 32 (2) orl cy, bit51 or direct bit to carry 2 1 (2) 21 (2) cy, bit or direct bit to carry 4 3 (2) 32 (2) cy, /bit51 or complemented direct bit to carry 2 1 (2) 21 (2) cy, /bit or complemented direct bit to carry 4 3 (2) 32 (2) mov cy, bit51 move direct bit to carry 2 1 (2) 21 (2) cy, bit move direct bit to carry 4 3 (2) 32 (2) bit51, cy move carry to direct bit 2 2 (3) 22 (3) bit, cy move carry to direct bit 4 4 (3) 33 (3)
25 rev. a - may 7, 1999 tsc80251g2d table 30. summary of exchange, push and pop instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. table 31. summary of conditional jump instructions (1/2) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. in internal execution only, add 1 to the number of states of the jump taken if the destination address is internal and odd. exchange bytes xch a, (a) ? src opnd exchange digit xchd a, (a) 3:0 ? src opnd 3:0 push push (sp) ? (sp) +1; ((sp)) ? src opnd; (sp) ? (sp) + size (src opnd) - 1 pop pop (sp) ? (sp) - size (dest opnd) + 1; dest opnd ? ((sp)); (sp) ? (sp) -1 mnemonic , (1) comments binary mode source mode bytes states bytes states xch a, rn acc and register 1 3 2 4 a, dir8 acc and direct address (on-chip ram or sfr) 2 3 (3) 23 (3) a, @ri acc and indirect address 1 4 2 5 xchd a, @ri acc low nibble and indirect address (256 bytes) 1 4 2 5 push dir8 push direct address onto stack 2 2 (2) 22 (2) #data push immediate data onto stack 4 4 3 3 #data16 push 16-bit immediate data onto stack 5 5 4 5 rm push byte register onto stack 3 4 2 3 wrj push word register onto stack 3 5 2 4 drk push double word register onto stack 3 9 2 8 pop dir8 pop direct address (on-chip ram or sfr) from stack 2 3 (2) 23 (2) rm pop byte register from stack 3 3 2 2 wrj pop word register from stack 3 5 2 4 drk pop double word register from stack 3 9 2 8 jump conditional on status jcc rel (pc) ? (pc) + size (instr); if [cc] then (pc) ? (pc) + rel mnemonic , (1) comments binary mode source mode bytes states bytes states jc rel jump if carry 2 1/4 (3) 2 1/4 (3) jnc rel jump if not carry 2 1/4 (3) 2 1/4 (3) je rel jump if equal 3 2/5 (3) 2 1/4 (3) jne rel jump if not equal 3 2/5 (3) 2 1/4 (3) jg rel jump if greater than 3 2/5 (3) 2 1/4 (3) jle rel jump if less than, or equal 3 2/5 (3) 2 1/4 (3) jsl rel jump if less than (signed) 3 2/5 (3) 2 1/4 (3) jsle rel jump if less than, or equal (signed) 3 2/5 (3) 2 1/4 (3) jsg rel jump if greater than (signed) 3 2/5 (3) 2 1/4 (3) jsge rel jump if greater than or equal (signed) 3 2/5 (3) 2 1/4 (3)
rev. a - may 7, 1999 26 tsc80251g2d table 32. summary of conditional jump instructions (2/2) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. 5. if this instruction addresses an i/o port (px, x= 0-3), add 3 to the number of states. add 5 if it addresses a peripheral sfr. 6. in internal execution only, add 1 to the number of states of the jump taken if the destination address is internal and odd. jump if bit jb , rel (pc) ? (pc) + size (instr); if [src opnd= 1] then (pc) ? (pc) + rel jump if not bit jnb , rel (pc) ? (pc) + size (instr); if [src opnd= 0] then (pc) ? (pc) + rel jump if bit and clear jbc , rel (pc) ? (pc) + size (instr); if [dest opnd= 1] then dest opnd ? 0 (pc) ? (pc) + rel jump if accumulator is zero jz rel (pc) ? (pc) + size (instr); if [(a)= 0] then (pc) ? (pc) + rel jump if accumulator is not zero jnz rel (pc) ? (pc) + size (instr); if [(a) 1 0] then (pc) ? (pc) + rel compare and jump if not equal cjne , , rel (pc) ? (pc) + size (instr); if [src opnd1 < src opnd2] then (cy) ? 1 if [src opnd1 3 src opnd2] then (cy) ? 0 if [src opnd1 1 src opnd2] then (pc) ? (pc) + rel decrement and jump if not zero djnz , rel (pc) ? (pc) + size (instr); dest opnd ? dest opnd -1; if [ j (z)] then (pc) ? (pc) + rel mnemonic , (1) comments binary mode (2) source mode (2) bytes states bytes states jb bit51, rel jump if direct bit is set 3 2/5 (3)(6) 3 2/5 (3)(6) bit, rel jump if direct bit of 8-bit address location is set 5 4/7 (3)(6) 4 3/6 (3)(6) jnb bit51, rel jump if direct bit is not set 3 2/5 (3)(6) 3 2/5 (3)(6) bit, rel jump if direct bit of 8-bit address location is not set 5 4/7 (3)(6) 4 3/6 (3) jbc bit51, rel jump if direct bit is set & clear bit 3 4/7 (5)(6) 3 4/7 (5)(6) bit, rel jump if direct bit of 8-bit address location is set and clear 5 7/10 (5)(6) 4 6/9 (5)(6) jz rel jump if acc is zero 2 2/5 (6) 2 2/5 (6) jnz rel jump if acc is not zero 2 2/5 (6) 2 2/5 (6) cjne a, dir8, rel compare direct address to acc and jump if not equal 3 2/5 (3)(6) 3 2/5 (3)(6) a, #data, rel compare immediate to acc and jump if not equal 3 2/5 (6) 3 2/5 (6) rn, #data, rel compare immediate to register and jump if not equal 3 2/5 (6) 4 3/6 (6) @ri, #data, rel compare immediate to indirect and jump if not equal 3 3/6 (6) 4 4/7 (6) djnz rn, rel decrement register and jump if not zero 2 2/5 (6) 3 3/6 (6) dir8, rel decrement direct address and jump if not zero 3 3/6 (4)(6) 3 3/6 (4)(6)
27 rev. a - may 7, 1999 tsc80251g2d table 33. summary of unconditional jump instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 3 to the number of states if the destination address is external. table 34. summary of call and return instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 5 to the number of states if intr= 1. absolute jump ajmp (pc) ? (pc) +2; (pc) 10:0 ? src opnd extended jump ejmp (pc) ? (pc) + size (instr); (pc) 23:0 ? src opnd long jump ljmp (pc) ? (pc) + size (instr); (pc) 15:0 ? src opnd short jump sjmp rel (pc) ? (pc) +2; (pc) ? (pc) +rel jump indirect jmp @a +dptr (pc) 23:16 ? ffh; (pc) 15:0 ? (a) + (dptr) no operation nop (pc) ? (pc) +1 mnemonic , (1) comments binary mode source mode bytes states bytes states ajmp addr11 absolute jump 2 3 (2)(3) 23 (2)(3) ejmp addr24 extended jump 5 6 (2)(4) 45 (2)(4) @drk extended jump (indirect) 3 7 (2)(4) 26 (2)(4) ljmp @wrj long jump (indirect) 3 6 (2)(4) 25 (2)(4) addr16 long jump (direct address) 3 5 (2)(4) 35 (2)(4) sjmp rel short jump (relative address) 2 4 (2)(4) 24 (2)(4) jmp @a +dptr jump indirect relative to the dptr 1 5 (2)(4) 15 (2)(4) nop no operation (jump never) 1 1 1 1 absolute call acall (pc) ? (pc) +2; push (pc) 15:0 ; (pc) 10:0 ? src opnd extended call ecall (pc) ? (pc) + size (instr); push (pc) 23:0 ; (pc) 23:0 ? src opnd long call lcall (pc) ? (pc) + size (instr); push (pc) 15:0 ; (pc) 15:0 ? src opnd return from subroutine ret pop (pc) 15:0 extended return from subroutine eret pop (pc) 23:0 return from interrupt reti if [intr= 0] then pop (pc) 15:0 if [intr= 1] then pop (pc) 23:0 ; pop (psw1) trap interrupt trap (pc) ? (pc) + size (instr); if [intr= 0] then push (pc) 15:0 if [intr= 1] then push (psw1); push (pc) 23:0 mnemonic , (1) comments binary mode source mode bytes states bytes states acall addr11 absolute subroutine call 2 9 (2)(3) 29 (2)(3) ecall @drk extended subroutine call (indirect) 3 14 (2)(3) 213 (2)(3) addr24 extended subroutine call 5 14 (2)(3) 413 (2)(3) lcall @wrj long subroutine call (indirect) 3 10 (2)(3) 29 (2)(3) addr16 long subroutine call 3 9 (2)(3) 39 (2)(3) ret return from subroutine 1 7 (2) 17 (2) eret extended subroutine return 3 9 (2) 28 (2) reti return from interrupt 1 7 (2)(4) 17 (2)(4) trap jump to the trap interrupt vector 2 12 (4) 111 (4)
rev. a - may 7, 1999 28 tsc80251g2d 8. programming and verifying non-volatile memory 8.1 internal features the internal non-volatile memory of the tsc80251g2d derivatives contains five different areas: l code memory l configuration bytes l lock bits l encryption array l signature bytes 8.1.1 eprom/otprom devices all the internal non-volatile memory but the signature bytes of the tsc87251g2d products is made of eprom cells. the signature bytes of the tsc87251g2d products are made of mask rom. the tsc87251g2d products are programmed and verified in the same manner as t emic s tsc87251g1a, using a single-pulse algorithm, which programs at v pp = 12.75v using only one 100 m s pulse per byte. this results in a programming time of less than 10 seconds for the 32 kbytes on-chip code memory. the eprom of the tsc87251g2d products in window package is erasable by ultra-violet radiation (1) (uv). uv erasure set all the eprom memory cells to one and allows a reprogramming. the quartz window must be covered with an opaque label (2) when the device is in operation. this is not so much to protect the eprom array from inadvertent erasure, as to protect the ram and other on-chip logic. allowing light to impinge on the silicon die during device operation may cause a logical malfunction. the tsc87251g2d products in plastic packages are one time programmable (otp). then an eprom cell cannot be reset by uv once programmed to zero. notes: 1. the recommended erasure procedure is exposure to ultra-violet light (at 2537 ?) to an integrated dose of at least 20 w-sec/cm 2 . exposing the eprom to an ultra-violet lamp of 12000 m w/cm 2 rating for 30 minutes should be sufficient. 2. erasure of the eprom begins to occur when the chip is exposed to light wavelength shorter than 4000 ?. since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. 8.1.2 mask rom devices all the internal non-volatile memory of tsc83251g2d products is made of mask rom cells. they can only be verified by the user, using the same algorithm as the eprom/otprom devices. 8.1.3 romless devices the tsc80251g2d products do not include on-chip configuration bytes, code memory and encryption array. they only include signature bytes made of mask rom cells which can be read using the same algorithm as the eprom/otprom devices. 8.2 security features in some microcontrollers applications, it is desirable that the users program code be secured from unauthorized access. the tsc83251g2d and tsc87251g2d offer two kinds of protection for program code stored in the on- chip array: l program code in the on-chip code memory is encrypted when read out for verification if the encryption array is programmed. l a three-level lock bit system restricts external access to the on-chip code memory.
29 rev. a - may 7, 1999 tsc80251g2d 8.2.1 lock bit system the tsc87251g2d products implement 3 levels of security for users program as described in table 35. the tsc83251g2d products implement only the first level of security. level 0 is the level of an erased part and does not enable any security features. level 1 locks the programming of the users internal code memory, the configuration bytes and the encryption array. level 2 locks the verifying of the users internal code memory. it is always possible to verify the configuration bytes and the lock bits. it is never possible to verify the encryption array. level 3 locks the external execution. table 35. lock bits programming notes: 1. returns encrypted data if encryption array is programmed. 2. returns non encrypted data. 3. x means dont care. level 2 always enables level 1, and level 3 always enables levels 1 and 2. the security level may be verified according to table 36. table 36. lock bits verifying note: 1. x means dont care. 8.2.2 encryption array the tsc83251g2d and tsc87251g2d products include a 128-byte encryption array located in non-volatile memory outside the memory address space. during verification of the on-chip code memory, the seven low-order address bits also address the encryption array. as the byte of the code memory is read, it is exclusive-nored (xnor) with the key byte from the encryption array. if the encryption array is not programmed (still all 1s), the user program code is placed on the data bus in its original, unencrypted form. if the encryption array is programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the key byte sequence. to preserve the secrecy of the encryption key byte sequence, the encryption array can not be verified. cautions: 1. when a movc instruction is executed, the content of the rom is not encrypted. in order to fully protect the user program code, the lock bit level 1 (see table 35) must always be set when encryption is used. 2. if the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with random byte values to prevent the encryption key sequence from being revealed. level lock bits lb[2:0] internal execution external execution verification programming external prom read (movc) 0 000 enable enable enable (1) enable enable (2) 1 001 enable enable enable (1) disable disable 2 01x (3) enable enable disable disable disable 3 1xx (3) enable disable disable disable disable level lock bits data (1) 0 xxxxx000 1 xxxxx001 2 xxxxx01x 3 xxxxx1xx
rev. a - may 7, 1999 30 tsc80251g2d 8.3 signature bytes the tsc80251g2d derivatives contain factory-programmed signature bytes. these bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. to read the signature bytes, perform the procedure described in section 8.5, using the verify signature mode (see table 39). signature byte values are listed in table 37. table 37. signature bytes (electronic id) 8.4 programming algorithm figure 9 shows the hardware setup needed to program the tsc87251g2d eprom/otprom areas: l the chip has to be put under reset and maintained in this state until the completion of the programming sequence. l psen# and the other control signals (ale and port 0) have to be set to a high level. l then psen# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence (see below). l the voltage on the ea# pin must be set to v dd . l the programming mode is selected according to the code applied on port 0 (see table 38). it has to be applied until the completion of this programming operation. l the programming address is applied on ports 1 and 3 which are respectively the most significant byte (msb) and the least significant byte (lsb) of the address. l the programming data are applied on port 2. l the eprom programming is done by raising the voltage on the ea# pin to v pp , then by generating a low level pulse on ale/prog# pin. l the voltage on the ea# pin must be lowered to v dd before completing the programming operation. l it is possible to alternate programming and verifying operation (see paragraph 8.5). please make sure the voltage on the ea# pin has actually been lowered to v dd before performing the verifying operation. l psen# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. signature address signature data vendor t emic 30h 58h architecture c251 31h 40h memory 32 kbytes eprom or otprom 60h f7h 32 kbytes maskrom or romless 77h revision tsc80251g2d derivative 61h fdh
31 rev. a - may 7, 1999 tsc80251g2d figure 9. setup for programming table 38. programming modes notes: 1. signature bytes are not user-programmable. 2. the ale/prog# pulse waveform is shown in figure 31 page 54. 8.5 verify algorithm figure 10 shows the hardware setup needed to verify the tsc87251g2d eprom/otprom or tsc83251g2d rom areas: l the chip has to be put under reset and maintained in this state until the completion of the verifying sequence. l psen# and the other control signals (ale and port 0) have to be set to a high level. l then psen# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the verifying sequence (see below). l the voltage on the ea# pin must be set to v dd and ale must be set to a high level. l the verifying mode is selected according to the code applied on port 0. it has to be applied until the completion of this verifying operation. l the verifying address is applied on ports 1 and 3 which are respectively the msb and the lsb of the address. l then device is driving the data on port 2. l it is possible to alternate programming and verification operation (see paragraph 8.4). please make sure the voltage on the ea# pin has actually been lowered to v dd before performing the verifying operation. l psen# and the other control signals have to be released to complete a sequence of verifying operations or a sequence of programming and verifying operations. rom area (1) rst ea#/vpp psen# ale/prog# (2) p0 p2 p1(msb) p3(lsb) on-chip code memory 1 v pp 0 1 pulse 68h data 16-bit address 0000h-7fffh (32 kbytes) configuration bytes 1 v pp 0 1 pulse 69h data config0: fff8h config1: fff9h lock bits 1 v pp 0 1 pulse 6bh x lb0: 0001h lb1: 0002h lb2: 0003h encryption array 1 v pp 0 1 pulse 6ch data 0000h-007fh vdd psen# ale/prog# ea#/vpp xtal1 vdd 4 to 12 mhz rst v pp 100 m s pulses vss/vss1/vss2 mode vdd a[7:0] a[14:8] data p0[7:0] p3[7:0] p1[7:0] p2[7:0] tsc87251g2d
rev. a - may 7, 1999 32 tsc80251g2d table 39. verifying modes note: 1. to preserve the secrecy of on-chip code memory when encrypted, the encryption array can not be verified. figure 10. setup for verifying rom area (1) rst ea#/vpp psen# ale/prog# p0 p2 p1(msb) p3(lsb) on-chip code memory 1 1 0 1 28h data 16-bit address 0000h-7fffh (32 kbytes) configuration bytes 1 1 0 1 29h data config0: fff8h config1: fff9h lock bits 1 1 0 1 2bh data 0000h signature bytes 1 1 0 1 29h data 0030h, 0031h, 0060h, 0061h vdd psen# ale/prog# ea#/vpp xtal1 vdd 4 to 12 mhz rst vss/vss1/vss2 mode vdd a[7:0] a[14:8] p0[7:0] p3[7:0] p1[7:0] tsc8x251g2d p2[7:0] data
rev. a - may 7, 1999 33 tsc80251g2d 9. absolute maximum rating and operating conditions 9.1 absolute maximum rating table 40. absolute maximum ratings 9.2 operating conditions table 41. operating conditions note: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. l storage temperature ......................... l voltage on any other pin to vss.... l i ol per i/o pin ................................. l power dissipation ............................. -65 to +150 c -0.5 to +6.5 v 15 ma 1.5 w l ambient temperature under bias commercial ....................................... industrial............................................ l v dd high speed versions ......................... low voltage versions....................... 0to+70 c -40 to +85 c 4.5 to 5.5 v 2.7 to 5.5 v
34 rev. a - may 7, 1999 tsc80251g2d 10. dc characteristics - commercial & industrial 10.1 dc characteristics: high speed versions - commercial & industrial table 42. dc characteristics; v dd = 4.5 to 5.5 v, t a = -40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) -0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) -0.5 0.3v dd v v il2 input low voltage (ea#) 0 0.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.3 0.45 1.0 vi ol = 100 m a (1)(2) i ol = 1.6 ma (1)(2) i ol = 3.5 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#, port 2 in page mode during external address) 0.3 0.45 1.0 vi ol = 200 m a (1)(2) i ol = 3.2 ma (1)(2) i ol = 7.0 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) v dd - 0.3 v dd - 0.7 v dd - 1.5 vi oh = -10 m a (3) i oh = -30 m a (3) i oh = -60 m a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) v dd - 0.3 v dd - 0.7 v dd - 1.5 vi oh = -200 m a i oh = -3.2 ma i oh = -7.0 ma v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2, 3) -50 m av in = 0.45 v i il1 logical 1 input current (nmi) +50 m av in =v dd i li input leakage current (port 0) 10 m a 0.45v rev. a - may 7, 1999 35 tsc80251g2d notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: ............................................. 10 ma maximum i ol per 8-bit port: port 0................. 26 ma ports 1-3............ 15 ma maximum total i ol for all: output pins ....... 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 5 v and t a =25 c. they are not tested and there is not guarantee on these values. 5. the input threshold voltage of scl and sda meets the i 2 c specification, so an input voltage below 0.3v dd will be recognized as a logic 0 while an input voltage above 0.7v dd will be recognized as a logic 1. note: 1. the clock prescaler is not used: f osc =f xtal . figure 11. i dd /i dl versus frequency; v dd = 4.5 to 5.5 v max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) 40 30 20 10 0 i dd /i dl (ma) frequency at x tal (1) (mhz) 2 4 6 8 10 12 14 16 18 20 22 24
36 rev. a - may 7, 1999 tsc80251g2d 10.2 dc characteristics: low voltage versions - commercial & industrial table 43. dc characteristics; v dd = 2.7 to 5.5 v, t a = -40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) -0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) -0.5 0.3v dd v v il2 input low voltage (ea#) 0 0.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.45 v i ol = 0.8 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#, port 2 in page mode during external address) 0.45 v i ol = 1.6 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) 0.9v dd vi oh = -10 m a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) 0.9v dd vi oh = -40 m a v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2 , 3 - await#) -50 m av in = 0.45 v i il1 logical 1 input current (nmi) +50 m av in =v dd i li input leakage current (port 0) 10 m a 0.45 v < v in rev. a - may 7, 1999 37 tsc80251g2d notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: ............................................. 10 ma maximum i ol per 8-bit port: port 0................. 26 ma ports 1-3............ 15 ma maximum total i ol for all: output pins ....... 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 3 v and t a =25 c. they are not tested and there is not guarantee on these values. 5. the input threshold voltage of scl and sda meets the i 2 c specification, so an input voltage below 0.3v dd will be recognized as a logic 0 while an input voltage above 0.7v dd will be recognized as a logic 1. note: 1. the clock prescaler is not used: f osc = f xtal . figure 12. i dd /i dl versus x tal frequency; v dd = 2.7 to 3.6 v max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) 15 10 5 0 i dd /i dl (ma) frequency at x tal (1) (mhz) 2468 14 10 12 16
38 rev. a - may 7, 1999 tsc80251g2d 10.3 dc characteristics: i dd, i dl and i pd test conditions figure 13. i dd test condition, active mode figure 14. i dl test condition, idle mode figure 15. i pd test condition, power-down mode vdd xtal2 vdd clock signal rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) i dd vdd all other pins are unconnected xtal2 vdd clock signal rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) i dl vdd all other pins are unconnected xtal2 vdd rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) i pd vdd all other pins are unconnected
rev. a - may 7, 1999 39 tsc80251g2d 11. ac characteristics - commercial & industrial 11.1 ac characteristics - external bus cycles definition of symbols table 44. external bus cycles timing symbol definitions timings test conditions: capacitive load on all pins= 50 pf. table 45 and table 46 list the ac timing parameters for the tsc80251g2d derivatives with no wait states. external wait states can be added by extending psen#/rd#/wr# and or by extending ale. in these tables, note 2 marks parameters affected by one ale wait state, and note 3 marks parameters affected by psen#/rd#/wr# wait states. figure 16 to figure 21 show the bus cycles with the timing parameters. signals conditions a address h high d data in l low l ale v valid q data out x no longer valid r rd#/psen# z floating w wr#
40 rev. a - may 7, 1999 tsc80251g2d table 45. bus cycles ac timings; v dd = 4.5 to 5.5 v, t a = -40 to 85 c notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2nt osc (n= 1..3). symbol parameter 12 mhz 16 mhz 24 mhz unit min max min max min max t osc 1/f osc 83 62 41 ns t lhll ale pulse width 78 58 38 ns (2) t avll address valid to ale low 78 58 37 ns (2) t llax address hold after ale low 19 11 3 ns t rlrh (1) rd#/psen# pulse width 162 121 78 ns (3) t wlwh wr# pulse width 165 124 81 ns (3) t llrl (1) ale low to rd#/psen# low 22 14 6 ns t lhax ale high to address hold 99 70 40 ns (2) t rldv (1) rd#/psen# low to valid data 146 104 61 ns (3) t rhdx (1) data hold after rd#/psen# high 0 0 0 ns t rhax (1) address hold after rd#/psen# high 0 0 0 ns t rlaz (1) rd#/psen# low to address float 0 0 0 ns t rhdz1 instruction float after rd#/psen# high 45 40 30 ns t rhdz2 data float after rd#/psen# high 215 165 115 ns t rhlh1 rd#/psen# high to ale high (instruction) 49 43 31 ns t rhlh2 rd#/psen# high to ale high (data) 215 169 115 ns t whlh wr# high to ale high 215 169 115 ns t avdv1 address (p0) valid to valid data in 250 175 105 ns (2)(3) t avdv2 address (p2) valid to valid data in 306 223 140 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 150 109 68 ns (3) t axdx data hold after address hold 0 0 0 ns t avrl (1) address valid to rd# low 100 70 40 ns (2) t avwl1 address (p0) valid to wr# low 100 70 40 ns (2) t avwl2 address (p2) valid to wr# low 158 115 74 ns (2) t whqx data hold after wr# high 90 69 32 ns t qvwh data valid to wr# high 133 102 72 ns (3) t whax wr# high to address hold 167 125 84 ns
rev. a - may 7, 1999 41 tsc80251g2d table 46. bus cycles ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2nt osc (n= 1..3). symbol parameter 12 mhz 16 mhz unit min max min max t osc 1/f osc 83 62 ns t lhll ale pulse width 72 52 ns (2) t avll address valid to ale low 71 51 ns (2) t llax address hold after ale low 14 6 ns t rlrh (1) rd#/psen# pulse width 163 121 ns (3) t wlwh wr# pulse width 165 124 ns (3) t llrl (1) ale low to rd#/psen# low 17 11 ns t lhax ale high to address hold 90 57 ns (2) t rldv (1) rd#/psen# low to valid data 133 92 ns (3) t rhdx (1) data hold after rd#/psen# high 0 0 ns t rhax (1) address hold after rd#/psen# high 0 0 ns t rlaz (1) rd#/psen# low to address float 0 0 ns t rhdz1 instruction float after rd#/psen# high 59 48 ns t rhdz2 data float after rd#/psen# high 225 175 ns t rhlh1 rd#/psen# high to ale high (instruction) 60 47 ns t rhlh2 rd#/psen# high to ale high (data) 226 172 ns t whlh wr# high to ale high 226 172 ns t avdv1 address (p0) valid to valid data in 289 160 ns (2)(3) t avdv2 address (p2) valid to valid data in 296 211 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 144 98 ns (3) t axdx data hold after address hold 0 0 ns t avrl (1) address valid to rd# low 111 64 ns (2) t avwl1 address (p0) valid to wr# low 111 64 ns (2) t avwl2 address (p2) valid to wr# low 158 116 ns (2) t whqx data hold after wr# high 82 66 ns t qvwh data valid to wr# high 135 103 ns (3) t whax wr# high to address hold 168 125 ns
42 rev. a - may 7, 1999 tsc80251g2d waveforms in non-page mode note: 1. the value of this parameter depends on wait states. see table 45 and table 46. figure 16. external bus cycle: code fetch (non-page mode) note: 1. the value of this parameter depends on wait states. see table 45 and table 46. figure 17. external bus cycle: data read (non-page mode) t avdv2 (1) t avdv1 (1) t llax t rhdz1 t rhdx t rhax t avrl (1) p2/a16/a17 p0 psen# ale t lhll (1) t rlrh (1) instruction in a15:8/a16/a17 t rlaz t llrl (1) t rhlh1 t rldv (1) t avll (1) t lhax (1) a7:0 d7:0 t avdv2 (1) t avdv1 (1) t llax t rhax t rhdx t rhdz2 t avll (1) t avrl (1) p2/a16/a17 p0 rd#/psen# ale t lhll (1) t rlrh (1) t lhax (1) data in a15:8/a16/a17 t rlaz t llrl (1) t rhlh2 t rldv (1) d7:0 a7:0
rev. a - may 7, 1999 43 tsc80251g2d note: 1. the value of this parameter depends on wait states. see table 45 and table 46. figure 18. external bus cycle: data write (non-page mode) waveforms in page mode notes: 1. the value of this parameter depends on wait states. see table 45 and table 46. 2. a page hit (i.e., a code fetch to the same 256-byte page as the previous code fetch) requires one state (2t osc ); a page miss requires two states (4t osc ). 3. during a sequence of page hits, psen# remains low until the end of the last page-hit cycle. figure 19. external bus cycle: code fetch (page mode) t whlh t avwl2 (1) t avwl1 (1) t lhax (1) t llax t whqx t whax p2/a16/a17 p0 wr# ale t lhll (1) t wlwh (1) data out a15:8/a16/a17 t avll (1) t qvwh a7:0 d7:0 t llax t avdv2 (1) t avdv1 (1) t lhax (1) t avrl (1) t rhdz1 t rlaz t axdx t avdv3 (1) p0/a16/a17 p2 psen# (3) ale t lhll (1) a7:0/a16/a17 t avll (1) t llrl (1) t rldv (1) page miss (2) page hit (2) t rhax a7:0/a16/a17 d7:0 d7:0 a15:8 instruction in instruction in t rhdx
44 rev. a - may 7, 1999 tsc80251g2d note: 1. the value of this parameter depends on wait states. see table 45 and table 46. figure 20. external bus cycle: data read (page mode) note: 1. the value of this parameter depends on wait states. see table 45 and table 46. figure 21. external bus cycle: data write (page mode) t avdv2 (1) t avdv1 (1) t llax t rhax t rhdx t rhdz2 t avll (1) t avrl (1) p0/a16/a17 p2 rd#/psen# ale t lhll (1) t rlrh (1) t lhax (1) data in a7:0/a16/a17 t rlaz t llrl (1) t rhlh2 t rldv (1) d7:0 a15:8 t whlh t avwl2 (1) t avwl1 (1) t lhax (1) t llax t whqx t whax p0/a16/a17 p2 wr# ale t lhll (1) t wlwh (1) data out a7:0/a16/a17 t avll (1) t qvwh a15:8 d7:0
rev. a - may 7, 1999 45 tsc80251g2d 11.2 ac characteristics - real-time synchronous wait state definition of symbols table 47. real-time synchronous wait timing symbol definitions timings table 48. real-time synchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c waveforms figure 22. real-time synchronous wait state: code fetch/data read signals conditions c wclk l low r rd#/psen# v valid w wr# x no longer valid y wait# symbol parameter min max unit t clyv wait clock low to wait set-up 0 t osc -20 ns t clyx wait hold after wait clock low 2wt osc + 5 (1+2w)t osc -20 ns t rlyv psen#/rd# low to wait set-up 0 t osc -20 ns t rlyx wait hold after psen#/rd# low 2wt osc + 5 (1+2w)t osc -20 ns t wlyv wr# low to wait set-up 0 t osc -20 ns t wlyx wait hold after wr# low 2wt osc + 5 (1+2w)t osc -20 ns state 1 state 2 state 3 state 1 (next cycle) t rlyx max t rlyx min t rlyv t clyv t clyx max p2 rd#/psen# ale wclk p0 wait# t clyx min rd#/psen# stretched a15:8 a7:0 d7:0 stretched a15:8 stretched a7:0
46 rev. a - may 7, 1999 tsc80251g2d figure 23. real-time synchronous wait state: data write 11.3 ac characteristics - real-time asynchronous wait state definition of symbols table 49. real-time asynchronous wait timing symbol definitions timings table 50. real-time asynchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c note: 1. n is the number of wait states added (n 3 1). waveforms figure 24. real-time asynchronous wait state timings signals conditions s psen#/rd#/wr# l low y await# v valid x no longer valid symbol parameter min max unit t slyv psen#/rd#/wr# low to wait set-up t osc -10 ns t slyx wait hold after psen#/rd#/wr# low (2n-1)t osc +10 ns (1) state 1 state 2 state 3 state 1 (next cycle) t wlyx max t wlyx min t wlyv t clyv t clyx max p2 rd#/psen# ale wclk p0 wait# t clyx min wr# stretched a7:0 d7:0 stretched a15:8 stretched t slyv t slyx rd#/psen#/wr# await#
rev. a - may 7, 1999 47 tsc80251g2d 11.4 ac characteristics - serial port in shift register mode definition of symbols table 51. serial port timing symbol definitions timings table 52. serial port ac timing -shift register mode; v dd = 2.7 to 5.5 v, t a = -40 to 85 c note: 1. for high speed versions only. waveforms note: 1. ti and ri are set during s1p1 of the peripheral cycle following the shift of the eight bit. figure 25. serial port waveforms - shift register mode signals conditions d data in h high q data out l low x clock v valid x no longer valid symbol parameter 12 mhz 16 mhz 24 mhz (1) unit min max min max min max t xlxl serial port clock cycle time 998 749 500 ns t qvxh output data setup to clock rising edge 833 625 417 ns t xhqx output data hold after clock rising edge 165 124 82 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 974 732 482 ns t xlxl t xhdv t xhdx t qvxh t xhqx set ti (1) set ri (1) valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 0 1 2 3 4 5 6 7
48 rev. a - may 7, 1999 tsc80251g2d 11.5 ac characteristics - sslc: i 2 c interface timings table 53. i 2 c interface ac timing; v dd = 2.7 to 5.5 v, t a = -40 to 85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 m s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maximum capacitance on bus-lines sda and scl= 400 pf. 4. t clcl =t osc = one oscillator clock period. waveforms figure 26. i 2 c waveforms symbol parameter input min max output min max t hd ; sta start condition hold time 14t clcl (4) 4.0 m s (1) t low scl low time 16t clcl (4) 4.7 m s (1) t high scl high time 14t clcl (4) 4.0 m s (1) t rc scl rise time 1 m s- (2) t fc scl fall time 0.3 m s 0.3 m s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) -t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 m s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) -t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 m s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 m s (1) t buf bus free time 14t clcl (4) 4.7 m s (1) t rd sda rise time 1 m s- (2) t fd sda fall time 0.3 m s 0.3 m s (3) t su ;sta t su ;dat2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t su ;dat1 t hd ;dat t su ;dat3 start or repeated start condition start condition stop condition repeated start condition
rev. a - may 7, 1999 49 tsc80251g2d 11.6 ac characteristics - sslc: spi interface definition of symbols table 54. spi interface timing symbol definitions timings table 55. spi interface ac timing; v dd = 2.7 to 5.5 v, t a = -40 to 85 c signals conditions c clock h high i data in l low o data out v valid s ss# x no longer valid z floating symbol parameter min max unit slave mode (1) t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch ,t slcl ss# low to clock edge 200 ns t ivcl ,t ivch input data valid to clock edge 100 ns t clix ,t chix input data hold after clock edge 100 ns t clov, t chov output data valid after clock edge 100 ns t clox ,t chox output data hold time after clock edge 0 ns t clsh ,t chsh ss# high after clock edge 0 ns t ivcl ,t ivch input data valid to clock edge 100 ns t clix ,t chix input data hold after clock edge 100 ns t slov ss# low to output data valid 130 ns t shox output data hold after ss# high 130 ns t shsl ss# high to ss# low (2) t ilih input rise time 2 m s t ihil input fall time 2 m s t oloh output rise time 100 ns t ohol output fall time 100 ns
50 rev. a - may 7, 1999 tsc80251g2d notes: 1. capacitive load on all pins= 200 pf in slave mode. 2. the value of this parameter depends on software. 3. capacitive load on all pins= 100 pf in master mode. waveforms note: 1. ss# handled by software. figure 27. spi master waveforms (sscpha= 0) master mode (3) t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl ,t ivch input data valid to clock edge 50 ns t clix ,t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 65 ns t clox ,t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 m s t ihil input data fall time 2 m s t oloh output data rise time 50 ns t ohol output data fall time 50 ns symbol parameter min max unit miso (input) sck (sscpol= 0) (output) ss# (1) (output) sck (sscpol= 1) (output) mosi (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
rev. a - may 7, 1999 51 tsc80251g2d note: 1. ss# handled by software. figure 28. spi master waveforms (sscpha= 1) note: 1. not defined but normally msb of character just received. figure 29. spi slave waveforms (sscpha= 0) miso (input) sck (sscpol= 0) (output) ss# (1) (output) sck (sscpol= 1) (output) mosi (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch t slcl t slch t chcl t clch mosi (input) sck (sscpol= 0) (input) ss# (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh
52 rev. a - may 7, 1999 tsc80251g2d note: 1. not defined but generally the lsb of the character which has just been received. figure 30. spi slave waveforms (sscpha= 1) t chcl t clch mosi (input) sck (sscpol= 0) (input) ss# (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch
rev. a - may 7, 1999 53 tsc80251g2d 11.7 ac characteristics - eprom programming and verifying definition of symbols table 56. eprom programming and verifying timing symbol definitions timings table 57. eprom programming ac timings; v dd = 4.5 to 5.5 v, t a =0to40 c table 58. eprom verifying ac timings; v dd = 4.5 to 5.5 v, v dd = 2.7 to 5.5 v, t a =0to40 c signals conditions a address h high e enable: mode set on port 0 l low g program v valid q data out x no longer valid s supply (v pp ) z floating symbol parameter min max unit t osc xtal1 period 83.5 250 ns t avgl address setup to prog# low 48 t osc t ghax address hold after prog# low 48 t osc t dvgl data setup to prog# low 48 t osc t ghdx data hold after prog# 48 t osc t elsh enable high to v pp 48 t osc t shgl v pp setup to prog# low 10 m s t ghsl v pp hold after prog# 10 m s t sleh enable hold after v pp 0ns t glgh prog# width 90 110 m s symbol parameter min max unit t osc xtal1 period 83.5 250 ns t avqv address to data valid 48 t osc t axqx address to data invalid 0 ns t elqv enable low to data valid 0 48 t osc t ehqz data float after enable 0 48 t osc
54 rev. a - may 7, 1999 tsc80251g2d waveforms figure 31. eprom programming waveforms figure 32. eprom verifying waveforms t sleh t elsh t dvgl t shgl t avgl t ghax t ghdx t glgh t ghsl v pp v dd v ss p1= a15:8 p3= a7:0 p2= d7:0 ea#/vpp ale/prog# p0 mode= 68h, 69h, 6bh or 6ch data address t ehqz t elqv t avqv t axqx p1= a15:8 p3= a7:0 p2= d7:0 p0 address mode= 28h, 29h or 2bh data
rev. a - may 7, 1999 55 tsc80251g2d 11.8 ac characteristics - external clock drive and logic level references definition of symbols table 59. external clock timing symbol definitions timings table 60. external clock ac timings; v dd = 4.5 to 5.5 v, t a = -40 to +85 c waveforms figure 33. external clock waveform note: during ac testing, all inputs are driven at v dd -0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 34. ac testing input/output waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. figure 35. float waveforms signals conditions c clock h high l low x no longer valid symbol parameter min max unit f osc oscillator frequency 24 mhz t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx 0.45 v v dd - 0.5 0.2 v dd + 0.9 0.2 v dd - 0.1 v ih min v il max inputs outputs v load v oh - 0.1 v v ol + 0.1 v v load + 0.1 v v load - 0.1 v timing reference points
rev. a - may 7, 1999 56 tsc80251g2d 12. packages 12.1 list of packages l pdil 40 l cdil 40 with window l plcc 44 l cqpj 44 with window l vqfp 44 (10 x 10) 12.2 pdil 40 - mechanical outline figure 36. plastic dual in line table 61. pdil package size mm inch min max min max a - 5.08 - .200 a1 0.38 - .015 - a2 3.18 4.95 .125 .195 b 0.36 0.56 .014 .022 b1 0.76 1.78 .030 .070 c 0.20 0.38 .008 .015 d 50.29 53.21 1.980 2.095 e 15.24 15.87 .600 .625 e1 12.32 14.73 .485 .580 e 2.54 b.s.c. .100 b.s.c. ea 15.24 b.s.c. .600 b.s.c. eb - 17.78 - .700 l 2.93 3.81 .115 .150 d1 0.13 - .005 -
57 rev. a - may 7, 1999 tsc80251g2d 12.3 cdil 40 with window - mechanical outline figure 37. ceramic dual in line table 62. cdil package size mm inch min max min max a - 5.71 - .225 b 0.36 0.58 .014 .023 b2 1.14 1.65 .045 .065 c 0.20 0.38 .008 .015 d - 53.47 - 2.105 e 13.06 15.37 .514 .605 e 2.54 b.s.c. .100 b.s.c. ea 15.24 b.s.c. .600 b.s.c. l 3.18 5.08 .125 .200 q 0.38 1.40 .015 .055 s1 0.13 - .005 - a 0-15 0-15 n40
rev. a - may 7, 1999 58 tsc80251g2d 12.4 plcc 44 - mechanical outline figure 38. plastic lead chip carrier table 63. plcc package size mm inch min max min max a 4.20 4.57 .165 .180 a1 2.29 3.04 .090 .120 d 17.40 17.65 .685 .695 d1 16.44 16.66 .647 .656 d2 14.99 16.00 .590 .630 e 17.40 17.65 .685 .695 e1 16.44 16.66 .647 .656 e2 14.99 16.00 .590 .630 e 1.27 bsc .050 bsc g 1.07 1.22 .042 .048 h 1.07 1.42 .042 .056 j 0.51 - .020 - k 0.33 0.53 .013 .021 nd 11 11 ne 11 11
59 rev. a - may 7, 1999 tsc80251g2d 12.5 cqpj 44 with window - mechanical outline figure 39. ceramic quad pack j table 64. cqpj package size mm inch min max min max a - 4.90 - .193 c 0.15 0.25 .006 .010 d - e 17.40 17.55 .685 .691 d1 - e1 16.36 16.66 .644 .656 e 1.27 typ .050 typ f 0.43 0.53 .017 .021 j 0.86 1.12 .034 .044 q 15.49 16.00 .610 .630 r 0.86 typ .034 typ n1 11 11 n2 11 11
rev. a - may 7, 1999 60 tsc80251g2d 12.6 vqfp 44 (10 x 10) - mechanical outline figure 40. shrink quad flat pack (plastic) table 65. vqfp package size mm inch min max min max a - 1.60 - .063 a1 0.64 ref .025 ref a2 0.64 ref .025ref a3 1.35 1.45 .053 .057 d 11.90 12.10 .468 .476 d1 9.90 10.10 .390 .398 e 11.90 12.10 .468 .476 e1 9.90 10.10 .390 .398 j 0.05 - .002 6 l 0.45 0.75 .018 .030 e 0.80 bsc .0315 bsc f 0.35 bsc .014 bsc
rev. a - may 7, 1999 61 tsc80251g2d 13. ordering information 13.1 tsc80251g2d romless note: 1. dry pack mandatory for vqfp package. 13.2 tsc83251g1d 16 kbytes mask rom notes: 1. dry pack mandatory for vqfp package. 2. xxx: means rom code, is cxxx in case of encrypted code. 13.3 tsc83251g2d 32 kbytes maskrom notes: 1. dry pack mandatory for vqfp package. 2. xxx: means rom code, is cxxx in case of encrypted code. temic part number rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc80251g2d-16cb romless 16 mhz, commercial 0 to 70 c, plcc 44 tsc80251g2d-24cb romless 24 mhz, commercial 0 to 70 c, plcc 44 tsc80251g2d-24ced romless 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc80251g2d-24ia romless 24 mhz, industrial -40 to 85 c, pdil 40 tsc80251g2d-24ib romless 24 mhz, industrial -40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial tsc80251g2d-l16cb romless 16 mhz, commercial, plcc 44 tsc80251g2d-l16ced romless 16 mhz, commercial, vqfp 44, dry pack (1) temic part number (2) rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc251g1dxxx-16cb 16k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxx-24cb 16k maskrom 24 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxx-24ced 16k maskrom 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc251g1dxxx-24ia 16k maskrom 24 mhz, industrial -40 to 85 c, pdil 40 tsc251g1dxxx-24ib 16k maskrom 24 mhz, industrial -40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial tsc251g1dxxx-l16cb 16k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxx-l16ced 16k maskrom 16 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) temic part number (2) rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc251g2dxxx-16cb 32k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g2dxxx-24cb 32k maskrom 24 mhz, commercial 0 to 70 c, plcc 44 tsc251g2dxxx-24ced 32k maskrom 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) TSC251G2DXXX-24IA 32k maskrom 24 mhz, industrial -40 to 85 c, pdil 40 tsc251g2dxxx-24ib 32k maskrom 24 mhz, industrial -40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial tsc251g2dxxx-l16cb 32k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g2dxxx-l16ced 32k maskrom 16 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1)
62 rev. a - may 7, 1999 tsc80251g2d 13.4 tsc87251g2d otprom note: 1. dry pack mandatory for vqfp package. 13.5 tsc87251g2d eprom - uv window package 13.6 options (please consult temic sales) rom code encryption tape & real or dry pack known good dice ceramic packages extended temperature range: -55 c to +125 c 13.7 starter kit 13.8 products marking note: 1. dry pack letter (d) not included in the marking. temic part number rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc87251g2d-16cb 32k otprom 16 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-24cb 32k otprom 24 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-24ced 32k otprom 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc87251g2d-24ia 32k otprom 24 mhz, industrial -40 to 85 c, pdil 40 tsc87251g2d-24ib 32k otprom 24 mhz, industrial -40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial tsc87251g2d-l16cb 32k otprom 16 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-l16ced 32k otprom 16 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) temic part number rom description high speed versions 4.5 to 5.5 v, industrial tsc87251g2d-24ic 32k eprom 24 mhz, industrial -40 to 85 c, window cqpj 44 tsc87251g2d-24ij 32k eprom 24 mhz, industrial -40 to 85 c, window cdil 40 low voltage versions 2.7 to 5.5 v, industrial tsc87251g2d-l16ic 32k eprom 16 mhz, commercial -40 to 85 c, window cqpj 44 temic part number description tsc80251-sk tsc80251 starter kit romless versions temic customer part number temic part number intel97 yyww . lot number mask rom versions temic temic part number (1) intel97 yyww . lot number otp versions temic temic part number (1) intel97 yyww . lot number m m m c c c
sales offices may 1999 63 sales locations europe sales offices finland temic nordic ab c/o atmel oy kappelitie 6b fin02200 tel: 358 9 4520 8219 fax: 358 9 529 619 france temic france les quadrants 3, avenue du centre b.p. 309 78054 st.quentinenyvelines cedex tel: 33 1 30 60 70 00 fax: 33 1 30 60 71 11 germany temic semiconductor gmbh erfurter strasse 31 85386 eching tel: 49 89 3 19 70 0 fax: 49 89 3 19 46 21 temic semiconductor gmbh kruppstrasse 6 45128 essen tel: 49 2 01 24 73 00 fax: 49 2 01 2 47 30 47 temic semiconductor gmbh theresienstrasse 2 74072 heilbronn tel: 49 71 31 67 3636 fax: 49 71 31 67 3163 italy temic italiana via grosio, 10/8 20151 milano tel: 39 02 38 03 71 fax: 39 02 38 03 72 34 spain temic iberica principe de vergara, 112 28002 madrid tel: 34 91 564 51 81 fax: 34 91 562 75 14 sweden temic nordic ab kavallerivaegen 24, rissne box 2042 17202 sundbyberg tel: 46 8 587 48 800 fax: 46 8 587 48 850 united kingdom temic u.k. ltd. easthampstead road bracknell, berkshire rg12 1lx tel: 44 1344 707 300 fax: 44 1344 427 371 north america sales offices western temic north america c/o atmel corporation 2325 orchard parkway san jose california 95131 tel: 1 408 441 0311 fax: 1 408 436 4200 eastern temic north america inc. 180 mount airy road, ste. 100 basking ridge new jersey 07920 tel: 1 908 630 9200 fax: 1 908 630 9201 asia pacific / japan sales offices china temic shanghai c/o atmel corp 4th floor, block a shanghai eastern business bldg 586 fanyu road, shanghai 200052 china tel: 86 21 6280 9241 fax: 86 21 6283 8816 hong kong temic hong kong ltd. c/o atmel asia ltd # 1216, chinachem golden plaza 77 mody road tsimhatsui east kowloon, hong kong tel: 852 23 789 789 fax: 852 23 755 733 japan temic semiconductors c/o atmel japan k.k. tonetsushinkawa bldg. 1248, shinkawa, chuku tokyo 1040033 tel: 81 3 3523 3551 fax: 81 3 3523 7581 rep. of singapore temic singapore pte ltd keppel building, #0300 25 tampines street 92 singapore 528877 tel: 65 260 8223 fax: 65 787 9819 korea temic korea ltd. suite 605, singsong bldg. 254 yoidodong youngdeungpoku 150010 seoul tel: 82 2 785 1136 fax: 82 2 785 1137 taiwan, r.o.c. temic taiwan, c/o atmel corp. 9f1 no.266 sec.1 wen hwa 2rd lin kon hsiang taipei hsien tel: 886 2 2609 5581 fax: 886 2 2600 2735

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